Integrated chips are formed by operating upon a semiconductor workpiece with a plurality of different processing steps. In general, the processing steps may include lithographic patterning to selectively mask one or more areas of a workpiece (e.g., a semiconductor substrate), implantations to modify electrical properties of a workpiece, etches to remove portions of a workpiece, and depositions to form one or more layers on a workpiece.
Deposition processes are widely used on varying surface topologies in both front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) processing. For example, in FEOL processing deposition processes may be used to form polysilicon material on a substantially flat substrate, while in BEOL processing deposition processes may be used to form metal layers within a cavity in a dielectric layer. Deposition processes may be performed by a wide range of deposition tools, including physical vapor deposition (PVD) tools, chemical vapor deposition (CVD) tools, atomic layer deposition (ALD) tools, etc.